Simple Bounds on Serial Signature Analysis Aliasing for Random Testing

Refined Bounds on Signature Analysis Aliasing for Random Testing

in previous work a simple bound, ~ + 2 , on the aliasing probability in serial signature analysis for a random test pattern of length L was derived. This simple bound is sharpened here by almost a factor of two. For serial signature analysis, it is shown that the I+& 1 aliasing probability is bounded above by = L ( E L small for large L ) for test lengths L less than the period, Lc, of the sign...

Parallel Signatur Analysis Design with Bounds on Aliasing

This paper presents parallel signature design techniques that guarantee the aliasing probability to be less than 2/L, where L is the test length. Using y signature samples, a parallel signature analysis design is proposed that guarantees the aliasing probability to be less than (y/L). Inaccuracies and incompleteness in previously published bounds on the aliasing probability are discussed. Simpl...

Signature Testing of Analog-to-digital Converters

− When testing an analog-to-digital converter (ADC) by automatic test equipment (ATE), the latter is capable of performing extensive processing of output responses of the ADC. This allows detection of virtually any fault. However, the cost of ATE is quite high. As well, the external bandwidth of ATE is normally lower than the internal bandwidth of the ADC being tested, which makes it difficult ...

Correction to the Proof of Theorem 2 in "Parallel Signature Analysis Design with Bounds on Aliasing"

Aliasing Probability Calculations in Testing Sequential Circuits

This paper focuses on testing sequential circuits using a simple form of signature analysis as a compaction technique. More specifically, the paper describes a systematic methodology for calculating the probability of aliasing when a randomly generated test input vector sequence is applied to a given finite state machine (FSM) and the final FSM output is used to verify the functionality of the ...